![]() ![]() In the RC oscillation mode, the quartz crystals function as the AC coupling capacitors. The actual startup mechanism is the excitation of the high-frequency (~1 MHz) RC oscillator mode. Because no additional load capacitors or phase-shifting resistors are used in the oscillator loop, the power dissipation of the oscillator is reduced. With the two quartz resonators (X1-X2) working in the serial resonance mode and two digital CMOS inverters (M3-M6) in the gain loop, the loop phase is zero and the loop gain is larger than unity for small signals, resulting in the proper conditions for oscillation start-up. The schematic of the proposed quartz oscillator is shown in Figure 1. In the current paper a quartz oscillator design without load capacitors is proposed, resulting in 0.12 μ W measured power dissipation at a power supply voltage 0.53 V. Therefore, circuits shown in cannot be seriously considered except for the most marginal applications despite having power dissipation below 0.1 μ W. However, reduced voltage swing on crystal is extremely detrimental to the phase noise and frequency stability. In, the power dissipation of the crystal oscillator was radically reduced by reducing the voltage swing at crystal terminals. However, in, the load network is not the same for the two gain stages, making it difficult to optimize both of the gain stages for low power. ![]() In, the load capacitors are integrated into the VLSI chip and the phase-shifting RC network is eliminated by using two inverting gain stages. As a consequence, precision load capacitors become necessary. Although the power spent charging and discharging load capacitors can be regenerated using a Pierce oscillator topology without phase-shifting resistors, or even differential architectures derived from LC-oscillators, such designs result in sensitivity of the output frequency on the nominal value of the load capacitors. Real power dissipation will be even larger due to the transistors switching and leakage losses. For the minimal value of C load = 8.5 pF in parallel with quartz resonator, f osc = 32,768 Hz and V dd = 0.5 V in the classical quartz oscillator (Pierce topology with phase-shifting resistors), the power loss due to the charging/discharging of the load capacitors cannot be reduced below 0.14 μ W. The secondary mechanism, important for the high-voltage oscillators, is the reduction of the slew rate dV dt at the input of the inverter, forcing the transistors of the inverter to run in the active mode, therefore dissipating additional crowbar current. The primary mechanism is the charging and discharging of the load capacitor through the resistive element of the inverter and phase-shifting resistor. The power loss due to the load capacitors occurs via two mechanisms. (1) assumes the load capacitors are charged or discharged twice per clock cycle with the rail-to-rail voltage swing, and all energy temporarily stored in load capacitors is lost. ![]()
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